Bonding structures and methods of forming bonding structures

ABSTRACT

A semiconductor structure includes a first substrate and a second substrate bonded over the first substrate. The first substrate includes a passivation layer formed over the first substrate. The passivation layer includes at least one first opening exposing a first bonding pad formed over the first substrate. The second substrate includes at least one second opening aligned with and facing the first opening.

This application is a division of U.S. patent application Ser. No.11/563,490, filed Nov. 27, 2006, which is expressly incorporated byreference herein in its entirety.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to semiconductor structures and methods offorming the semiconductor structures, and more particularly to bondingstructures and methods of forming bonding structures.

2. Description of the Related Art

With advances associated with electronic products, semiconductortechnology has been widely applied in manufacturing memories, centralprocessing units (CPUs), liquid crystal displays (LCDs), light emissiondiodes (LEDs), laser diodes and other devices or chipsets. In order toachieve high-integration and high-speed goals, dimensions ofsemiconductor integrated circuits continue to shrink. Various materialsand techniques have been proposed to achieve these integration and speedgoals and to overcome manufacturing obstacles associated therewith. Inorder to shrink die size, a through wafer via (TWV) technique has beenused in this field.

FIGS. 1A-1E are cross-sectional views showing a prior art method offorming TWV.

As shown in FIG. 1A, a multi-level interconnect structure 110 comprisingmetal layers 115 is formed over a substrate 100. Bonding pads 125 areformed over the multi-level interconnect structure 110. A passivationlayer 120 is formed over the bonding pads 125 and includes openings 130formed therein partially exposing the bonding pads 125.

In FIG. 1B, a dummy substrate 150 is bonded on the passivation layer 120by a thermal tape 155. The dummy substrate 150 serves as a carrier forgrinding the substrate 100. After the thermal tape bonding, thesubstrate 100 is grinded, thereby forming a remaining substrate 100 ahaving a thickness of about 150 μm as shown in FIG. 1C.

Turning to FIG. 1D, TWVs 160 are formed within the substrate 100 a,contacting with the metal layers 115. TWVs 160 provide electricalconnection between the metal layers 115 to which diodes or circuits arecoupled and another substrate (not shown). TWVs 160 usually include adiffusion barrier layer and a metal layer which is formed by a chemicalvapor deposition (CVD) or physical vapor deposition (PVD) step having aprocessing temperature of about 300° C. The diffusion barrier layer canbe a conductive layer such as a metal nitride layer or a dielectriclayer such as a silicon nitride layer. The thermal tape 155, however,cannot tolerate such a processing temperature, and the thermal tape 155may dissolve and/or fail to adequately bond the dummy structure 150 tothe passivation layer 120. The dummy substrate 150 may separate from thepassivation layer 120 in subsequent processing steps, such as a chemicalmechanical planarization (CMP) processing step for planarizing the metallayer provided for the formation of the TWVs 160. Consequently, thesubstrate 100 a can be damaged by the CMP step.

From the foregoing, semiconductor structures and methods of forming thesemiconductor structures are desired.

SUMMARY OF THE INVENTION

In accordance with some exemplary embodiments, a semiconductor structureincludes a first substrate and a second substrate bonded over the firstsubstrate. The first substrate includes a passivation layer formed overthe first substrate. The passivation layer includes at least one firstopening exposing a first bonding pad formed over the first substrate.The second substrate includes at least one second opening aligned withand facing the first opening.

In accordance with some exemplary embodiments, a method of forming asemiconductor structure is provided. A dummy substrate is bonded over afirst substrate. The first substrate comprises a passivation layerformed thereover. The passivation layer comprises at least one firstopening exposed a first bonding pad formed over the first substrate. Thedummy substrate comprises at least one second opening aligned with andfacing the first opening. The first substrate is thinned using the dummysubstrate as a carrier for the first substrate. The dummy substrate isthinned to expose the first opening and second opening.

The above and other features will be better understood from thefollowing detailed description of the preferred embodiments of theinvention that is provided in connection with the accompanying drawings.

BRIEF DESCRIPTION OF THE DRAWINGS

Following are brief descriptions of exemplary drawings. They are mereexemplary embodiments and the scope of the present invention should notbe limited thereto.

FIGS. 1A-1E are cross-sectional views showing a prior art method offorming TWV.

FIGS. 2A-2D are schematic cross-sectional views of an exemplary methodof bonding a thinned dummy substrate over a substrate.

FIGS. 2E-2F are schematic cross-sectional views of an exemplary methodof forming at least one through wafer via (TWV) 260 within the thinnedsubstrate 200 a shown in FIG. 2C.

FIGS. 2G-2H are schematic cross-sectional views of an exemplary methodof forming a plurality of bump structures.

FIGS. 3A-3D are schematic cross-sectional views showing the die of FIG.2D mounted over a substrate.

FIG. 3E is a schematic cross-sectional view of a die as shown in FIG. 2Hflip mounted over a substrate.

FIG. 3F shows an enlarged partial top view of region 301 of FIG. 3B.

DESCRIPTION OF THE PREFERRED EMBODIMENT

This description of the exemplary embodiments is intended to be read inconnection with the accompanying drawings, which are to be consideredpart of the entire written description. In the description, relativeterms such as “lower,” “upper,” “horizontal,” “vertical,” “above,”“below,” “up,” “down,” “top” and “bottom” as well as derivatives thereof(e.g., “horizontally,” “downwardly,” “upwardly,” etc.) should beconstrued to refer to the orientation as then described or as shown inthe drawing under discussion. These relative terms are for convenienceof description and do not require that the apparatus be constructed oroperated in a particular orientation.

FIGS. 2A-2D are schematic cross-sectional views of an exemplary methodof bonding a thinned dummy substrate over a substrate.

Referring to FIG. 2A, a substrate 200 comprises a multi-level structure210 formed thereover. The substrate 200 can be a silicon substrate,III-V compound substrate, display substrate such as a liquid crystaldisplay (LCD), plasma display, electro luminescence (EL) lamp display,or light emitting diode (LED) substrate (collectively referred to as,substrate 200), for example. The substrate 200 may have an initialthickness between about 600 μm and about 1,200 μm. On the substrate 200,various active devices such as MOSFET and bipolar, passive devices suchas resistors, capacitors and inductors, diodes, devices and/or circuits(not shown) are formed. The multi-level structure 210 may comprise atleast one conductive layer 215 (e.g., metal layers, vias, contacts,damascene structures, dual damascene structures, combinations thereof,or the like) and at least one dielectric layer (not labeled) (e.g.,oxide layer, nitride layer, oxynitride layer, low-k dielectric layer,combinations thereof, or the like), as will be familiar to those in theart. The multi-level structure 210 is formed to provide interconnectionamong the diodes, transistors, devices and/or other circuit devicesformed on the substrate 200. These devices and the multi-level structure210 can be formed, for example, by photolithographic processing steps,etch processing steps, implantation processing steps, metallizationprocessing steps, deposition processing steps, cleaning processing stepsand/or combinations thereof or the like.

At least one bonding pad 225 is formed over the multi-level structure210, providing electrical connection with another substrate (not shown).The bonding pads 225 may comprise a copper (Cu) layer, aluminum (Al)layer, AlCu layer, combinations thereof or the like. The bonding pad 225may be formed by a physical vapor deposition (PVD) step, chemical vapordeposition (CVD) step, electrochemical plating step, electroless platingstep, combinations thereof or the like.

A passivation layer 220 is formed over the multi-level structure 210.The passivation layer 220 may comprise at least one opening 230 formedover the bonding pad 225. The passivation layer 220 may comprise anoxide layer, nitride layer, oxynitride layer, polyimide layer, PIQ™(provided by Hitachi Chemical Co., Ltd. of Tokyo, Japan), combinationsthereof or the like. The passivation layer 220 may be formed by, forexample, a CVD step, spin-coating step, combinations thereof or thelike. The openings 230 may be formed by a photolithographic step and anetch step, for example. The openings 230 are provided such that thebonding pads 225 are exposed for wire bonding or flip bonding to anothersubstrate (not shown). In some embodiments, the openings 230 may have alength and width between about 30 μm and about 45 μm or an equivalentdiameter.

Referring to FIG. 2B, a dummy substrate 250 is bonded over the substrate200, i.e., the passivation layer 220. The dummy substrate 250 maycomprise at least one opening 255 formed therein. The openings 255 canbe, for example, trench, square openings, rectangular openings,combinations thereof or the like. The openings 255 correspond to oralign with and face the openings 230, wherein the openings 255 aresubstantially equal to or larger at least in width, length and/ordiameter than the openings 230. For example, the openings 255 may havelength and/or width substantially equal to those of the openings 230,and the openings 255 may have a depth of about 10 um or more. The depthis determined based on the final thickness (after thinning) of the dummysubstrate 250 required. In other embodiments, the openings 255 may havelength and/or width larger than those of the openings 230, and have adepth of about 20 μm or more.

The dummy substrate 250 can be a silicon substrate, III-V compoundsubstrate, glass substrate or other substrates (collectively referred toas, dummy substrate 250), for example. In some embodiments, the dummysubstrate 250 does not include any integrated devices, diodes and/orcircuits formed therein or thereon. The dummy substrate 250 may comprisea silicon layer, oxide layer, nitride layer, oxynitride layer,combinations thereof or other material layer which has a materialpropensity for bonding with the passivation layer 220. For example, inembodiments, the dummy substrate 250 is a bare silicon wafer and thepassivation layer 220 comprises an oxide layer such as silicon oxide.After a thermal treatment and/or plasma treatment, dangling bonds areformed on the surfaces of the silicon wafer and the oxide layer. By abonding step, dangling bonds on the surfaces of the silicon substrateand the oxide layer may be bonded to each other by Van Der Waal force,for example.

The dummy substrate 250 may be bonded over the passivation layer 200 by,for example, a fusion bonding step, tape bonding step, combinationsthereof or the like. For embodiments using the tape-bonding technique, atape (not shown) is formed between the passivation layer 220 and thedummy substrate 250 such that they are bonded to each other. Due to itsmaterial properties, the tape may not tolerate a high-thermal processingstep, e.g., a thermal processing step having a processing temperature ofabout 200° C. or higher. In embodiments using a fusion bonding step, thesurfaces of the dummy substrate 250 and/or the passivation layer 220 aresubjected to plasma treatments. After the plasma treatments, the dummysubstrate 250 can be bonded over the passivation layer 220 at a bondingtemperature ranging from about 20° C. to about 500° C. Since thepassivation layer 220 and the dummy substrate 250 are bonded without anadhesive layer, e.g., tape, the bonded structure can tolerate asubsequent high-thermal processing step. The bonding step is describedin more detail in connection with FIG. 2B.

Referring to FIG. 2C, the dummy substrate 250, sometimes referred toherein as a carrier layer, is provided as a carrier for thinning thesubstrate 200. The thinning step may comprise, for example, a grindingprocessing step comprising a chemical mechanical planarization (CMP)step. The remaining, thinned substrate 200 a may have a thicknessbetween about 50 μm and about 300 μm. After thinning the substrate 200,the remaining substrate 200 a can be used as a carrier for use duringthinning the dummy substrate 250 as shown in FIG. 2D.

The dummy substrate 250 is thinned until the openings 255 and 230 areexposed. In other words, the bonding pads 225 are exposed through thesubstrate 250 a for bonding with another substrate (not shown) such as achip carrier, for example, an organic substrate, ceramic substrate orleadframe by gold wires. As described above, the openings 255 may beabout 10 um or more in depth. The thinned dummy substrate 250 a may havea thickness between about 5 μm and about 100 μm. In other embodiments,the openings 255 may have a depth of about 10 μm or more within thedummy substrate 250. However, the dummy substrate 250 may be thinnedsuch that the final depth of the openings 255 within the thinned dummysubstrate 250 is about 10 μm or more. The thickness of the thinned dummysubstrate 250 a is controlled so that top corners of the thinned dummysubstrate 250 a do not interfere with a subsequent wire bonding step asshown in FIG. 3A.

FIGS. 2E-2F are schematic cross-sectional views of an exemplary methodof forming at least one through wafer via (TWV) 260 within the thinnedsubstrate 200 a shown in FIG. 2C.

Referring to FIG. 2E, TWVs 260 are formed within the remaining substrate200 a, electrically connecting with the conductive layers 215. Theprocess of forming the TWVs 260 may comprise, for example, forming aplurality of openings (not shown) within the thinned substrate 200 a topartially expose the conductive layers 215; forming a substantiallyconformal barrier layer (not shown) within the openings; forming ametal-containing layer (not shown) over the barrier layer; and/orremoving portions of the barrier layer and the metal-containing layer,thereby forming the TWVs 260. The openings may be formed by, forexample, a photolithographic step and an etch step. The barrier layermay comprise, for example, an oxide layer, nitride layer, oxynitridelayer, metal nitride layer, titanium (Ti) layer, titanium nitride (TiN)layer, tantalum (Ta) layer, tantalum nitride (TaN) layer, combinationsthereof or the like. The barrier layer can be formed by, for example, aCVD step, PVD step, combinations thereof or the like. Themetal-containing layer may comprise, for example, a Cu layer, Al layer,AlCu layer, combinations thereof or the like. The metal-containing layermay be formed by, for example, a CVD step, PVD step, electrochemicalplating step, electroless plating step, combinations thereof or thelike. The removing step may comprise an etch step, chemical-mechanicalplanarization (CMP) step, combinations thereof or the like.

For embodiments forming a radio frequency (RF) chip, the conductivelayers 215 can be any metal layer (but generally referred to as Metal-1layers) which are coupled to emitters of RF devices. The TWVs 260 arethen mounted over another substrate (not shown), electrically connectingthe conductive layers 215 with the substrate for grounding.

For embodiments forming TWVs 260, it is preferred that the bonding stepdescribed above in connection with FIG. 2B is a fusion bonding step.Since the fusion bonding step does not use an adhesive layer, such as atape, the structure shown in FIG. 2E can tolerate the processingtemperatures encountered when the barrier layer and/or metal-containinglayer are formed at a temperature of about 200° C. or more.

After the formation of the TWVs 260, the dummy substrate 250 issubjected to a thinning process as described above in connection withFIG. 2D. The structure with the thinned dummy substrate 250 a is shownin FIG. 2F.

The bonded substrates shown in FIGS. 2D and 2F are subjected to a dicingstep along scribe lines (not shown) for forming individual dies.Processes for singulating dies are familiar to those in the art. Thedicing step may comprise, for example, a diamond sawing step, lasersawing step, water sawing step, combinations thereof or the like. Afterthe dicing step, the individual die is mounted over another substrate byadditional processing steps as described in FIGS. 3A-3E.

FIGS. 2G-2H are schematic cross-sectional views of an exemplary methodof forming a plurality of bump structures.

In order to form a bump structure, a plurality of openings 230, 231, 255and 256 are formed in the passivation layer 220 and the thinned dummysubstrate 250 a, respectively. The openings 231 and 256 shown in FIG. 2Gcan be formed in the same manner as the openings 230 and 255 describedabove in connection with FIGS. 2A-2D. The openings 231 and 256 areprovided such that an array of bumps can be formed over the activeregion (not shown) of the substrate 200 a.

Conductive structures 240 are then formed within the openings 230, 231,255 and 256 as shown in FIG. 2H. Bumps 245 are formed over the surfacesof the conductive structures 240 and the thinned dummy substrate 250 a.The conductive structures 240 may comprise, for example, a Cu layer, Allayer, AlCu layer, solder, combinations thereof or the like, and may beformed by an electrochemical plating step, CVD step, PVD step,electroless plating step, combinations thereof or the like. The bumps245 may comprise, for example, an Al layer, Cu layer, AlCu layer, gold(Au) layer, solder, combinations thereof or the like, and may be formedby an electrochemical plating step, electroless plating step,combinations thereof or the like. The plating step forms the bumps 245on the conductive structures 240, but not on the exposed surface of thethinned dummy substrate 250 a. In some embodiments, bumps may comprisethe conductive structures 240 and the bump 245 according to appliedprocesses.

For these embodiments, the openings 255, 256 may have a depth of about50 μm or more. By forming the conductive structures 240 within theopenings 230, 255 and 231, 256, the conductive structures 240 have athickness of about 50 μm or more. This thickness of the conductivestructures 240 contributes to a desired reliability when the bumps 245are bonded to another substrate, even if the bumps 245 have a thicknessof about 50 μm or less. The combined thickness of the bumps 245 andconductive structures 240 is greater than 50 μm, making the structureless susceptible to stresses associated with the prior art, as describedin more detail below. In some embodiments, the conductive structures 240may extend over or recess below the top surface of the thinned dummysubstrate 250 a.

A dense array of bump structures can be formed using the structures andmethods described in these embodiments. In a traditional bump structure,a spherical bump must have a thickness of about 50 μm or more in orderto ensure a desired bonding reliability. Due to its shape, the sphericalbump also has a width which is the same as its thickness. If a spacebetween two bonding pads is about 50 μm or less, two spherical bumpsformed on the bonding pads may contact to each other. Unlike thetraditional bump structure, the openings 255, 256 having a depth ofabout 50 μm or more, e.g., 100 μm or more, can accommodate theconductive structures 240 with a thickness of about 50 μm or more. Withthe addition of the conductive structures 240, the bumps 245 formedthereover may have a thickness of about 50 μm or less without bondingreliability concerns because of the additional thickness of theconductive structures 245, i.e., the total thickness of the structures240 and 245 is greater than 50 μm. In addition, since the bumps 245 canstill be about 50 μm or less in width, a dense array of the bumps 245can be achieved and the space between bonding pads 225 can be reduced.Therefore, the chip size with the bump structure is reduced.

FIGS. 3A-3D are schematic cross-sectional views showing the die of FIG.2D mounted over a substrate.

As shown in FIG. 3A, the substrate 200 a is mounted over a substrate 370(e.g., a chip carrier as set forth above in connection with FIGS. 2A-2D)under which a plurality of ball grid array (BGA) balls 390 are formed.The substrate 370 may comprise at least one bonding pad 375 formedthereover. The bonding pads 225 are wire bonded to the respectivebonding pads 375 for electrical connection between the devices, diodesand/or circuits formed over the substrate 200 a and optionally over thesubstrate 370 by wires 380 through the openings 230 and 255. In someembodiments, the substrate 370 may be a silicon substrate, III-Vcompound substrate, display substrate such as a liquid crystal display(LCD), plasma display, electro luminescence (EL) lamp display, lightemitting diode (LED) substrate, plastic substrate, ceramic substrate, aprinted circuit board (PCB) or the like. Accordingly, electrical signalsgenerated from the devices formed over the substrate 200 a can betransmitted to the pads 375 through the wires 380, and further to theBGA balls 390 through a conductive pattern (e.g., a routing on thesubstrate 370) and structure (not shown) formed over or within thesubstrate 370.

For some embodiments, it is preferred that the thickness of the thinneddummy substrate 250 a is controlled so that corners 251 of the thinneddummy substrate 250 a do not interfere with the wire bonding. It isnoted that the thinned dummy substrate 250 a may be provided as a heatspreader through which heat generated from the operations of the diodes,devices and/or circuits formed over the substrate 200 a can bedissipated. In some embodiments, the thinned dummy substrate 250 a maycomprises at least one conductive structure, e.g., TWV, (not shown)formed therethrough for thermal dissipation and/or electricalinterconnection if another substrate is mounted over the thinned dummysubstrate 250 a. In some embodiments, a heat sinker (not shown) may beformed over the thinned dummy substrate 250 a to enhance heatdissipation, if the mounting of the heat sinker does not interfere withthe wire bonding.

In some embodiments, the openings 255 are larger in cross-sectional areathan the openings 230. For example, as shown in FIG. 3B, the openings255′ may extend beyond the opening 230 to the edge of the thinned dummysubstrate 250 a such that no portion of the thinned dummy substrate 250a remains over the periphery of the die 200 a, e.g., scribe line area,in the area where a wire bond is formed. This feature is better shown inFIG. 3F, which is an enlarged partial top view of region 301 of FIG. 3B.Compared with the structure shown in FIG. 3A, the wide openings 255′shown in FIG. 3B effectively avoid any corner interference with the wirebonds 380′ from the thinned dummy substrate 250 a at the edge of the die200 a. In addition, in this embodiment, the height of the wires 380 mayalso be reduced.

FIG. 3C shows the die from FIG. 2F, which has TWVs 260, mounted over asubstrate layer including substrate portions 370 a-370 c. Forembodiments forming a RF device, the substrate sections 370 a-370 c maycomprise a lead frame substrate, for example. The TWVs 360 electricallyconnect the conductive layers 215 and the substrate section 370 b forgrounding. The substrate sections 370 a and 370 c are isolated from thesubstrate section 370 b for providing input/output (I/O) bonding betweenthe bonding pads 325 and 375 by the wires 380. As described above inconnection with FIGS. 3A-3B, wide openings 255′ and/or a heat sinker(not shown) can be incorporated into the structure shown in FIG. 3C.

Referring to FIG. 3D, a substrate 395 is mounted over the thinned dummylayer 250 a. The substrate 395 may comprise a passivation layer 397formed thereover. The passivation layer 397 may comprise a plurality ofopenings (not labeled) exposing bonding pads 399 formed over thesubstrate 395. The passivation layer 397 and the bonding pads 399 may bethe same as, or similar to, the passivation layer 220 and the bondingpads 225, respectively, as described above in connection with FIG. 2A.In some embodiments, the substrate 395 is the same as, or similar to,the substrate 200 a described above.

In some embodiments, wide openings 255′ have dimensions such that themounting of the substrate 395 does not interfere with the wire bonding.In addition, the thinned dummy substrate 250 a may serve as a spacer forseparating the substrates 200 a and 395. The thinned dummy substrate 250a may have a thickness of about 50 μm or more such that the mounting ofthe substrate 395 does not interfere with or contact the wires 380. Asset forth above, the thinned dummy substrate 250 a may comprise at leastone conductive structure (not shown) formed therethrough. The conductivestructure may provide an electrical connection between the substrate 200a and the substrate 395.

FIG. 3E is a schematic cross-sectional view of a die as shown in FIG. 2Hflip mounted over a substrate. As described above in connection withFIG. 2H, a flip chip mounting with a dense bump array can be achievedwith improved bonding reliability by bonding the die of FIG. 2H to thesubstrate 370.

Although the present invention has been described in terms of exemplaryembodiments, it is not limited thereto. Rather, the appended claimsshould be construed broadly to include other variants and embodiments ofthe invention which may be made by those skilled in the field of thisart without departing from the scope and range of equivalents of theinvention.

1. A semiconductor structure, comprising: a first substrate comprising apassivation layer formed thereover, the passivation layer comprising atleast one first opening exposing a bonding pad formed over the firstsubstrate; and a second substrate bonded over the passivation layer, thesecond substrate comprising at least one second opening substantiallyaligned with and facing the first opening.
 2. The semiconductorstructure of claim 1, wherein the second substrate has a thicknessbetween about 5 μm and about 100 μm.
 3. The semiconductor structure ofclaim 1, wherein the second opening is substantially equal to or largerthan the first opening in area.
 4. The semiconductor structure of claim1 further comprising a third substrate upon which the first substrate ismounted, the third substrate comprising at least one second bonding padformed thereover, wherein the first bonding pad is wire bonded to thesecond bonding pad through the first opening and the second opening. 5.The semiconductor structure of claim 4, wherein the first substratefurther comprises at least one through wafer via (TWV) formed therein,and the second substrate is bonded over the passivation layer with afusion bond.
 6. The semiconductor structure of claim 4 furthercomprising a fourth substrate mounted over the second substrate, whereinthe second substrate serves as a spacer between the fourth substrate andthe first substrate.
 7. The semiconductor structure of claim 1, whereinthe second opening extends completely through the second substrate andat least one conductive structure is formed within the first opening andsecond opening, wherein the conductive structure is flip bonded over athird substrate.
 8. The semiconductor structure of claim 7 furthercomprising at least one bump formed over the conductive structure. 9.The semiconductor structure of claim 1, wherein the second openingextends beyond the first opening to an edge of the second substrate. 10.The semiconductor structure of claim 1, wherein the first substratecomprises at least one through wafer via (TWV) formed therein; and thesecond substrate is bonded over the passivation layer with a fusionbond.
 11. The semiconductor structure of claim 10, wherein the secondsubstrate has a thickness between about 5 μm and about 100 μm.
 12. Thesemiconductor structure of claim 10 further comprising a third substrateupon which the first substrate is mounted, the third substratecomprising at least one second bonding pad formed thereover, wherein thebonding pad exposed in the first opening is wire bonded to the secondbonding pad through the first opening and the second opening.
 13. Asemiconductor structure, comprising: a first substrate; a passivationlayer formed over the first substrate, the passivation layer comprisingat least one first opening in which a first bonding pad is formed, thefirst opening having a first sidewall surrounding the first opening; adummy substrate formed of a separate piece of material from the firstsubstrate and the passivation layer, the dummy substrate bonded over thepassivation layer, the dummy substrate comprising at least one secondopening therein, the second opening having a second sidewall extendingfrom a surface of the dummy substrate facing the passivation layer to aface of the dummy substrate opposite the passivation layer, the secondopening aligned with and facing the first opening; the first substratehaving a planarized surface facing away from the dummy substrate; andthe dummy substrate having a planarized surface that exposes the firstopening through the second opening.
 14. The semiconductor structure ofclaim 13 further comprising a third substrate upon which the firstsubstrate is mounted; and a fourth substrate mounted over the dummysubstrate, wherein the dummy substrate serves as a spacer between thefourth substrate and the first substrate.
 15. The semiconductorstructure of claim 13, wherein the second opening is substantially equalto or larger than the first opening in area.
 16. The semiconductorstructure of claim 13, wherein the first substrate further comprises atleast one through wafer via (TWV) formed therein, and the dummysubstrate is bonded over the passivation layer with a fusion bond. 17.The semiconductor structure of claim 13, wherein at least one conductivestructure is formed within the first opening and second opening, furthercomprising a third substrate over which the conductive structure is flipbonded.
 18. A semiconductor structure, comprising: a first substrate; apassivation layer formed over the first substrate, the passivation layercomprising at least one first opening in which a first bonding pad isformed, the first opening having a first sidewall surrounding the firstopening; a dummy substrate formed of a separate piece of material fromthe first substrate and the passivation layer, the dummy substratebonded over the passivation layer, the dummy substrate having a firstsurface facing the passivation layer and a second surface opposite thefirst surface, the dummy substrate comprising at least one secondopening therein, the second opening having a second sidewall extendingfrom the first surface partially through the dummy substrate, the secondopening having a base between the first and second surfaces, the secondopening aligned with and facing the first opening; the first substratehaving a planarized surface facing away from the dummy substrate. 19.The semiconductor structure of claim 18, wherein the second opening issubstantially equal to or larger than the first opening in area.
 20. Thesemiconductor structure of claim 18, wherein the first substrate furthercomprises at least one through wafer via (TWV) formed therein, and thedummy substrate is bonded over the passivation layer with a fusion bond.